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vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 1 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 microbuck ? SIC403 6 a, 28 v integrated buck re gulator with programmable ldo description the vishay siliconix SIC403 is an advanced stand-alone synchronous buck regulator featuring integrated power mosfets, bootstrap switch, and a programmable ldo in a space-saving mlpq 5 x 5 - 32 pin package. the SIC403 is capable of operating with all ceramic solutions and switching frequencies up to 1 mhz. the programmable frequency, synchronous operation and selectable power-save allow operation at high efficiency across the full range of load current. the internal ldo may be used to supply 5 v for the gate drive circuits or it may be bypassed with an external 5 v for optimum efficiency and used to drive external n-channel mosfets or other loads. additional features include cycle-by- cycle current limit, voltage soft-start, under-voltage protection, programmable over-current protection, soft shutdown and selectable power-save. the vishay siliconix SIC403 also provides an enable input and a power good output. features ? halogen-free according to iec 61249-2-21 definition ? high efficiency > 95 % ? 6 a continuous output current capability ? integrated bootstrap switch ? programmable 200 ma ldo with bypass logic ? temperature compensated current limit ? pseudo fixed-frequency adaptive on-time control ? all ceramic solution enabled ? programmable input uvlo threshold ? independent enable pin for switcher and ldo ? selectable ultra-sonic power-save mode ? programmable soft-start ? soft-shutdown ? 1 % internal reference voltage ? power good output ? under and over voltage protection ? compliant to rohs directive 2002/95/ec applications ? notebook, desktop, and server computers ? digital hdtv and digital consumer applications ? networking and telecommunication equipment ? printers, dsl, and stb applications ? embedded applications ? point of load power supplies typical application circuit product summary input voltage range 3 v to 28 v output voltage range 0.75 v to 5.5 v operating frequency 200 khz to 1 mhz continuous output current 6 a peak efficiency 95 % at 300 khz package mlpq 5 mm x 5 mm pad 1 a g n d lx pad 3 lx pad 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 t o n a g n d e n \ps v lx i lim p good bst v i n fbl a g n d v dd v out fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 24 lx 23 22 e n l v i n v out v out p good 3.3 v e n /ps v (tri-state) ldo_e n SIC403 (mlp 5 x 5-32l) p g n d 31 30 29 25 26 27 2 8 32
www.vishay.com 2 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pin configuration (top view) pad 1 a g n d lx pad 3 lx pad 2 v i n p g n d lx p g n d p g n d p g n d p g n d p g n d 17 1 8 19 20 21 to n a g n d e n \ps v lx i lim p good bst v i n fbl a g n d v dd v out fb 1 2 3 4 5 7 6 8 ss p g n d v i n v i n v i n n c lx n c 9 10 11 12 13 14 15 16 p g n d 24 lx 23 22 e n l 31 30 29 25 26 27 2 8 32 pin description pin number symbol description 1fb feedback input for switching regulator. connect to an external resistor divider from output to program output voltage. 2v out output voltage input to the controller. additi onally may be used to by pass ldo to supply v dd directly. 3v dd bias for internal logic circuitry and gate drivers. connect to external 5v po wer supply or configure the internal ldo for 5 v. 4, 30, pad 1 a gnd analog ground 5fbl feedback input for internal ldo. connect to an external resistor divider from v dd to a gnd to program ldo output. 6, 9-11, pad 2 v in power stage input (hs fet drain) 7 ss connect to an external capacitor to a gnd to program softstart ramp 8 bst bootstrap pin. a capacitor is connected between bst and lx to provide hs driver voltage. 12 nc not internally connected 13, 23-25, 28, pad 3 lx switching node (hs fet source and ls fet drain) 14 nc not internally connected 15-22 p gnd power ground (ls fet source) 26 p good open-drain power good indicator. exte rnally pull-up resi stor is required. 27 i lim connect to an external resistor between i lim and lx to program over current limit 29 en/psv tri-state pin. pull low to a gnd to disable the regulator. float to enable forced continuous current mode. pull high to v dd to enable power save mode. 31 t on connect to an external resistor to a gnd program on-time 32 enl enable input for internal ldo. pull down to a gnd to disable internal ldo. ordering information part number package SIC403cd-t1-ge3 mlpq55-32 SIC403db evaluation board
document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 3 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 functional block diagram stresses beyond those listed under "absolute maximum ratings" may c ause permanent damage to the device. these are stress rating s only, and functional operation of the device at thes e or any other conditions beyond those indi cated in the operational sections of t he specifications is not implied. exposure to absolute ma ximum rating/conditions for extended peri ods may affect device reliability. note: for proper operation, the device should be used within the recommended conditions. gate dri v e control on-time generator + - zero cross detector fb comparator soft start reference v dd 26 29 a g n d 4, 30, pad 1 p good control and stat u s e n /ps v 1 31 2 3 fb t o n v out v alley1-limit bypass comparator a b y ldo 32 e n l v i n v dd mux v dd dl 27 8 bst lx i lim p g n d v i n v i n v dd 15 to 22 13, 23 to 25, 2 8 , pad 3 6, 9-11, pad 2 v dd 5 fbl 7 ss absolute maximum ratings (t a = 25 c, unless otherwise noted) parameter symbol min. max. unit lx to p gnd voltage v lx - 0.3 + 30 v lx to p gnd voltage (transient - 100 ns) v lx - 2 + 30 v in to p gnd voltage v in - 0.3 + 30 en/psv, p good , i lim , to a gnd - 0.3 v dd + 0.3 bst bootstrap to lx; v dd to p gnd - 0.3 + 6 a gnd to p gnd v ag-pg - 0.3 + 0.3 en/psv, p good , i lim , v out , v ldo , fb, fbl to gnd - 0.3 + (v dd + 0.3) t on to p gnd - 0.3 + (v dd - 1.5) bst to p gnd - 0.3 + 35 recommended operating conditions parameter symbol min. typ. max. unit input voltage v in 328 v v dd to p gnd v dd 35.5 v out to p gnd v out 0.75 5.5 thermal resistance ratings parameter symbol min. typ. max. unit storage temperature t stg - 40 + 150 c maximum junction temperature t j - 150 operation junction temperature t j - 25 + 125
www.vishay.com 4 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. this device is esd sensitive. use of standard esd handling precautions is required. b. calculated from package in still air, mounted to 3 x 4.5 (i n), 4 layer fr4 pcb with therma l vias under the exposed pad per j esd51 standards. exceeding the above specific ations may result in permanent damage to the devic e or device malfunction. operation outside of the parameters specififed in the electrical charac teristics section is not recommended. thermal resistance, junction-to-ambient b high-side mosfet low-side mosfet pwm controller and ldo thermal resistance 25 20 50 c/w peak ir reflow temperature t reflow - 260 c thermal resistance ratings electrical specifications parameter symbol test conditions unless specified v in = 12 v, v dd = 5 v, t a = + 25 c for typ., - 25 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit input supplies v in uvlo threshold voltage a v in_uv+ sensed at enl pin, rising edge 2.4 2.6 2.95 v v in_uv- sensed at enl pin, falling edge 2.235 2.4 2.565 v in uvlo hysteresis v in_uv_hy en/psv = high 0.2 v dd uvlo threshold voltage v dd_uv+ measured at v dd pin, rising edge 2.5 2.9 3 v dd_uv- measured at v dd pin, falling edge 2.4 2.7 2.9 v dd uvlo hysteresis v dd_uv_hy 0.2 v in supply current i in en/psv, enl = 0 v, v in = 28 v 8.5 20 a standby mode: enl = v dd , en/psv = 0 v 130 v dd supply current i vdd en/psv, enl = 0 v 3 7 en/psv = v dd , no load (f sw = 25 khz), v fb > 750 mv b 2 ma f sw = 250 khz, en/psv = floating, no load b 10 controller fb on-time threshold v fb-th static v in and load, - 40 c to + 85 c 0.7425 0.750 0.7599 v frequency range b f pwm continuous mode 200 1000 khz bootstrap switch resistance 10 ? timing on-time t on continuous mode operation v in = 15 v, v out = 5 v, r ton = 300 k ? 2386 2650 2915 ns minimum on-time b t on 80 minimum off-time b t off 320 soft start soft start time b t ss i out = i lim /2 1.7 ms analog inputs/outputs v out input resistance r o-in 500 k ? current sense zero-crossing detector threshold voltage v sense-th lx-p gnd - 3.5 0.5 + 4.7 mv power good power good threshold voltage pg_v th_upper v fb > internal reference 750 mv + 20 % power good threshold voltage pg_v th_lower v fb < internal reference 750 mv - 10 start-up delay time pg_t d c ss = 10 nf 12 ms fault (noise-immunity) delay time b pg_i cc v en = 0 v 5 s power good leakage current pg_i lk v en = 0 v 1 a
document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 5 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes: a. v in uvlo is programmable using a resistor divider from v in to enl to a gnd . the enl voltage is compared to an internal reference. b. guaranteed by design. c. the switch-over threshold is the maximum voltage diff erential between the v ldo and v out pins which ensures that v ldo will internally switch-over to v out . the non-switch-over threshold is the minimum voltage diff erential between the v ldo and v out pins which ensures that v ldo will not switch-over to v out . d. the ldo drop out voltage is the voltage at which the ldo output drops 2 % below th e nominal regulation point. power good on-resistance pg_r ds-on v en = 0 v 10 ? fault protection i lim source current i lim 8a valley current limit r ilim = 6 k ??? v dd = 5 v 6a output under-voltage fault v ouv_fault v fb with respect to internal 500 mv reference, 8 consecutive clocks - 25 % smart power-save protection threshold voltage b p save_vth v fb with respect to internal 500 mv reference + 10 % over-voltage protection threshold v fb with respect to internal 500 mv reference + 20 over-voltage fault delay b t ov-delay 5s over temperature shutdown b t shut 10 c hysteresis 150 c logic inputs/outputs logic input high voltage v in+ en, enl, psv 1 v logic input low voltage v in- 0.4 en/psv input bias current i en- en/psv = v dd or a gnd - 10 + 10 a enl input bias current v in = 28 v 11 18 fbl, fb input bias current fbl_i lk fbl, fb = v dd or a gnd - 1 + 1 linear dropout regulator vldo accuracy vldo acc v ldo load = 10 ma 4.85 5 5.15 v ldo current limit ldo_i lim start-up and foldback, v in = 12 v 85 ma operating current limit, v in = 12 v 134 200 v ldo to v out switch-over threshold c v ldo-bps - 50 + 50 mv v ldo to v out non-switch-over threshold c v ldo-nbps - 550 + 550 v ldo to v out switch-over resistance r ldo v out = 5 v 2 ? ldo drop out voltage d from v in to v vldo , v vldo = + 5 v, i vldo = 100 ma 1.2 v electrical specifications parameter symbol test conditions unless specified v in = 12 v, v dd = 5 v, t a = + 25 c for typ., - 25 c to + 85 c for min. and max., t j = < 125 c min. typ. max. unit
www.vishay.com 6 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics efficiency vs. i out (in continuous conduction mode) v out vs. i out (in continuous conduction mode) v out vs. v in at i out = 0 a (in continuous conduction mode, fsw = 500 khz) 0 10 20 30 40 50 60 70 80 90 0.01 0.1 1 10 efciency (%) i out (a) v in = 12 v, v out = 1 v, fsw = 500 khz 0.992 0.994 0.996 0.998 1 1.002 1.004 1.006 01234567 v out (v) v in = 12 v, v out = 1 v, fsw = 500 khz i out (a) 0.998 1 1.002 1.004 1.006 1.008 1.010 1.012 5 7 9 11131517192123 v out (v) v in (v) v out = 1 v, fsw = 500 khz, continuous conduction mode efficiency vs. i out (in power-save-mode) v out vs. i out (in power-save-mode) v out vs. v in at i out = 6 a (in continuous conduction mode, fsw = 500 khz) efciency (%) i out (a) 0.1 0.01 1 10 90 80 70 60 50 40 30 20 10 0 v in = 12 v, v out = 1 v, fsw = 500 khz 0.992 0.994 0.996 0.998 1 1.002 1.004 1.006 1.008 v out (v) 06 5 4 37 2 1 i out (a) v in = 12 v, v out = 1 v, fsw = 500 khz 0.95 0.96 0.97 0.98 0.99 1 1.01 1.02 1.03 1.04 1.05 v out (v) v out = 1 v, fsw = 500 khz, continuous conduction mode 5 7 9 11 13 15 17 19 23 21 v in (v)
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 7 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics v out vs. v in (i out = 0 a in power-save-mode) v out ripple vs. v in (i out = 0 a in continuous conduction mode) fsw vs. i out (in continuous conduction mode) 0.9 0.95 1 1.05 1.1 6 8 10 12 14 16 18 20 22 24 v out (v) v in (v) v out = 1 v, fsw = 500 khz, power saving mode 0 5 10 15 20 25 30 35 0 5 10 15 20 25 v out ripple (mv) v in (v) v out =1 v, i out = 0 a, fsw = 500 khz fsw (khz) i out (a) 350 370 390 410 430 450 470 490 510 530 550 01234567 v in = 12 v, v out = 1 v v out ripple vs. v in (i out = 6 a in continuous conduction mode) v out ripple vs. v in (i out = 0 a in powersavemode) fsw vs. i out (in powersavemode) 0 5 10 15 20 25 30 35 40 0 5 10 15 20 25 v out ripple (mv) v in (v) v out = 1 v, i out = 6 a, fsw = 500 khz 0 5 10 15 20 25 30 35 40 6 8 10 12 14 16 18 20 v out ripple (mv) v in (v) v out = 1 v, i out = 0 a, fsw = 500 khz 0 100 200 300 400 500 600 01 234567 fsw (khz) i out (a) v in = 12 v, v out = 1 v
www.vishay.com 8 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics v out ripple in power save mode (no load) (v in = 12 v, v out = 1 v) transient response in continuous conduction mode (6 a to 0.2 a) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in power save mode (6 a to 0.2 a) (v in = 12 v, v out = 1 v, fsw = 500 khz at 6 a) ch2 : output ripple voltage (20mv/div) ch1 : lx switching node (5v/div) time: 20 s/div ch3 : output current (2a/div) ch2 : output voltage (50mv/div) time: 5 s/div ch3 : output current (2a/div) ch2 : output voltage (50mv/div) time: 10 s/div v out ripple in continuous conduction mode (no oad) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in continuous conduction mode (0.2 a to 6 a) (v in = 12 v, v out = 1 v, fsw = 500 khz) transient response in power save mode (0.2 a to 6 a) (v in = 12 v, v out = 1 v, fsw = 500 khz at 6 a) ch2 : output ripple voltage (20mv/div) ch1 : lx switching node (5v/div) time: 2 s/div ch3 : output current (2a/div) ch2 : output voltage (50mv/div) time: 5 s/div ch3 : output current (2a/div) ch2 : output voltage (50mv/div) time: 10 s/div
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 9 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics start-up with v in ramping up (v in = 12 v, v out = 1 v, fsw = 500 khz) ch4 : vin (5v/div) ch2 : vout (500mv/div) ch3 : power good (5v/div) ch1 : switching node (5v/div) time: 10 ms/div overcurrent protection (v in = 12 v, v out = 1 v, fsw = 500 khz ) ch4 : iout (10a/div) ch2 : vout (1v/div) ch3 : power good (5v/div) ch1 : switching node (10v/div) time: 10 ms/div efficiency with 12 v in , 5 v out , 300 khz 70 75 80 85 90 95 100 01234 5 6 7 efciency (%) i out (a) v in = 12 v, v out = 5 v, fsw = 300 khz
www.vishay.com 10 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 applications information SIC403 synchronous buck converter the SIC403 is a step down synchronous buck dc/dc converter with integrated power fets and programmable ldo. the SIC403 is capable of 6 a operation at very high efficiency in a tiny 5 mm x 5 mm - 32 pin package. the programmable operating frequency range of 200 khz to 1 mhz, enables the user to optimize the solution for minimum board space and optimum efficiency. the buck controller employs pseudo-fixed frequency adaptive on-time control. this control scheme allows fast transient response thereby lowering the size of the power components used in the system. input voltage range the SIC403 requires two input supplies for normal operation: v in and v dd . v in operates over the wide range from 3 v to 28 v. v dd requires a 5 v supply input that can be an external source or the internal ldo configured to supply 5 v. pseudo-fixed frequency ad aptive on-time control the pwm control method used for the SIC403 is pseudo-fixed frequency, adapt ive on-time, as shown in figure 1. the ripple voltage generated at the output capacitor esr is used as a pwm ramp signal. this ripple is used to trigger the on-time of the controller. the adaptive on-time is dete rmined by an internal oneshot timer. when the one-shot is trig gered by the output ripple, the device sends a single on-time pulse to the highside mosfet. the pulse period is determined by v out and v in ; the period is proportional to output voltage and inversely proportional to input voltage. with this adaptive on-time arrangement, the device auto matically anticipates the on-time needed to regulate v out for the present v in condition and at the selected frequency. the adaptive on-time control has significant advantages over traditional control methods used in the controllers today. ? reduced component count by eliminating dcr sense or current sense resistor as no need of a sensing inductor current. ? reduced saves external components used for compensation by eliminating the no error amplifier and other components. ? ultra fast transient response because of fast loop, absence of error amplifier speeds up the transient response. ? predictable frequency spread because of constant on-time architecture. ? fast transient response enables operation with minimum output capacitance overall, superior performance compared to fixed frequency architectures. on-time one-shot generator (t on ) and operating frequency the SIC403 have an internal on-time one-shot generator which is a comparator th at has two inputs. the fb comparator output goes high when v fb is less than the internal 750 mv reference. this feeds into the gate drive and turns on the high-side mosfet, and also starts the one-shot timer. the one-shot timer uses an internal comparator and a capacitor. one comparator input is connected to v out , the other input is connected to the capacitor. when the on-time begins, the internal capacitor charges from zero volts through a current which is proportional to v in . when the capacitor voltage reaches v out , the on-time is completed and the high-side mosfet turns off. the figure 2 shows the on-chip implementation of on-time generation. this method automatically produces an on-time that is proportional to v out and inversely proportional to v in . the SIC403 uses an external resistor to set the ontime which indirectly sets the frequency. the on-time can be programmed to provide operating frequency from 200 khz to 1 mhz using a resistor between the t on pin and ground. the resistor value is selected by the following equation. figure 1 - output ripple and pwm control method v i n c i n v lx q1 q2 l esr + fb v lx t o n v fb c out v out fb threshold figure 2 - on-time generation fb 750 m v - + v out v i n r ton on-time = k x r ton x ( v out/ v i n ) fb comparator one-shot timer gate dri v es dh dl q1 q2 l q1 esr fb v out c out v lx + r ton = (t o n - 10 ns) x v i n 25 pf x v out
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 11 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 the maximum r ton value allowed is shown by the following equation. v out voltage selection the switcher output voltage is regulated by comparing v out as seen through a resistor divider at the fb pin to the internal 750 mv reference voltage, see figure 3. as the control method regulates the valley of t he output ripple voltage, the dc output voltage v out is off set by the output ripple according to the following equation. v out = 0.75 x (1 + r 1 /r 2 ) + v ripple /2 enable and power-save inputs the en/psv and enl inputs are used to enable or disable the switching regulator and the ldo. when en/psv is low (grounded) , the switching regulator is off and in its lowest power state. when off, the output of the switching regulator soft-discharges the output into a 15 ? internal resistor via the v out pin. when en/psv is allowed to float, the pin voltage will float to 1.5 v. the switching regulator turns on with power-save disabled and all switching is in forced continuous mode. when en/psv is high (above 2 v), the switching regulator turns on with ultra-sonic power-save enabled. the SIC403 ultra-sonic power-save operation maintains a minimum switching frequency of 25 khz, for applications with stringent audio requirements. the enl input is used to control the internal ldo. this input serves a second function by acting as a v in uvlo sensor for the switching regulator. the ldo is off when enl is low (grounded). when enl is a logic high but below the v in uvlo threshold (2.6 v typical), then the ldo is on and the s witcher is off. when enl is above the v in uvlo threshold, the ldo is enabled and the switcher is also enabled if the en/psv pin is not grounded. forced continuous mode operation the SIC403 operates the swit cher in forced continuous mode (fcm) by floating the en /psv pin (see figure 4). in this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross-conduction. this feature results in uniform frequency across the full load range with the trade-off being poor efficiency at light loads due to the high-frequency switching of the mosfets. ultrasonic power-save operation the SIC403 provides ultra- sonic power-save operation at light loads, with the minimu m operating frequency fixed at 25 khz. this is accomplished using an internal timer that monitors the time between consecutive high-side gate pulses. if the time exceeds 40 s, dl drives high to turn the low-side mosfet on. this draws current from v out through the inductor, forcing both v out and v fb to fall. when v fb drops to the 750 mv threshold, the next dh on-time is triggered. after the on-time is comple ted the high-side mosfet is turned off and the low-side mosfet turns on, the low-side mosfet remains on until the inductor current ramps down to zero, at which point the lo w-side mosfet is turned off. figure 3 - output voltage selection r ton_max = v i n _mi n 15 a v out r 1 r 2 to fb pin figure 4 - forced continuous mode operation figure 5 - ultrasonic power-save operation fb ripple v oltage ( v fb ) ind u ctor c u rrent dc load c u rrent fb threshold (750 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold dl dri v es high w hen on-time is completed. dl remains high u ntil v fb falls to the fb threshold. fb ripple v oltage ( v fb ) ind u ctor c u rrent (0a) fb threshold (750 m v ) dh dl on-time (t o n ) dh on-time is triggered w hen v fb reaches the fb threshold after the 40 s time-o u t, dl dri v es high if v fb has not reached the fb threshold. minim u m f s w ~ 25 khz
www.vishay.com 12 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 because the on-times are forc ed to occur at intervals no greater than 40 s, the frequency will not fall below ~ 25 khz. figure 5 shows ultra-sonic power-save operation. benefits of ultr asonic power-save having a fixed minimum frequency in power-save has some significant advantages as below: ? the minimum frequency of 25 khz is outside the audible range of human ear. this makes the operation of the SIC403 very quiet. ? the output voltage ripple seen in power-save mode is significant lower than conventional power-save, which improves efficiency at light loads. ? lower ripple in power-save also makes the power component selection easier. figure 6 shows the behavior under power-save and continuous conduction mode at light loads. smart power-save protection active loads may leak current from a higher voltage into the switcher output. under light load conditions with power-save-power-save enabled, this can force v out to slowly rise and reach the over-voltage threshold, resulting in a hard shutdown. smart power-sav e prevents this condition. when the fb voltage exceeds 10 % above nominal (exceeds 825 mv), the device immediatel y disables power-save, and dl drives high to turn on the low-side mosfet. this draws current from v out through the inductor and causes v out to fall. when v fb drops back to the 750 mv trip point, a normal t on switching cycle begins. this method prevents a hard ovp shutdown and also cycles energy from v out back to v in . it also minimizes operating power by avoiding forced conduction mode operation. figure 7 shows typical waveforms for the smart power-save feature. current limit protection the SIC403 features programmable current limit capability, which is accomplished by using the r ds(on) of the lower mosfet for current sensing. th e current limit is set by r ilim resistor. the r ilim resistor connects from the i lim pin to the lx pin which is also the drain of the low-side mosfet. when the low-side mosfet is on, an internal ~ 10 a current flows from the i lim pin and the r ilim resistor, creating a voltage drop across the resistor. while the low-side mosfet is on, the inductor current flows through it and creates a voltage across the r ds(on) . the voltage across the mosfet is negative with respect to ground. if this mosfet voltage drop exceeds the voltage across r ilim , the voltage at the i lim pin will be negative and current limit will activate. the current limit then keeps the low-side mosfet on and will not allow another high-side on-time, until the current in the low-side mosfet reduces enough to bring the i lim voltage back up to zero. this method regulates the inductor valley current at the level shown by i lim in figure 8. setting the valley current limit to 6 a results in a 6 a peak inductor current plus peak ripple current. in this situation, the average (load) current through the inductor is 6 a plus one-half the peak-to-peak ripple current. the internal 8 a current source is temperature compensated at 4100 ppm in order to provide tracking with the r ds(on) . the r ilim value is calculated by the following equation. r ilim = 1176 x i lim figure 6 - ultrasonic power-save operation mode figure 7 - smart power-save figure 8 - valley current limit v out drifts u p to d u e to leakage c u rrent flo w ing into c out smart po w er sa v e threshold ( 8 25 m v ) fb threshold dh and dl off high-side dri v e (dh) lo w -side dri v e (dl) n ormal v out ripple v out discharges v ia ind u ctor and lo w -side mosfet single dh on-time p u lse after dl t u rn-off n ormal dl p u lse after dh on-time p u lse dl t u rns on w hen smart psa v e threshold is reached dl t u rns off fb threshold is reached i peak i load i lim time ind u ctor c u rrent
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 13 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 note that because the low-side mosfet with low r ds(on) is used for current sensing, the pcb layout, solder connections, and pcb connection to the lx node must be done carefully to obtain good results. refer to the layout guidelines for information. soft-start of pwm regulator SIC403 has a programmable soft-start time that is controlled by an external capacitor at the ss pin. after the controller meets both uvlo and en/psv thresholds, the controller has an internal current source of 2.75 a flowing through the ss pin to charge the capacitor. during the start up process, 50 % of the voltage at the ss pi n is used as the reference for the fb comparator. the pwm comparator issues an on-time pulse when the voltage at the fb pin is less than 50 % of the ss pin. as result, the output voltage follows the ss start voltage. the output volt age reaches and maintains regulation when the soft start voltage is > 1.5 v. the time between the first lx pulse and when v out meets regulation is the soft start time (t ss ). the calculation for the soft-start time is shown by the following equation: power good output the power good (p good ) output is an open-drain output which requires a pull-up resistor. when the output voltage is 10 % below the nominal voltage, p good is pulled low. it is held low until the output voltage returns above - 8 % of nom- inal. p good is held low during start-up and will not be allowed to transition high until soft-start is completed (when v fb reaches 750 mv) and typically 2 ms has passed. p good will transition low if the v fb pin exceeds + 20 % of nominal, which is also the over-voltage shutdown threshold (900 mv). p good also pulls low if the en/psv pin is low when v dd is present. output over-vol tage protection over-voltage protection becomes active as soon as the device is enabled. the threshold is set at 750 mv + 20 % (900 mv). when v fb exceeds the ovp threshold, dl latches high and the low-side mosfet is turned on. dl remains high and the cont roller remains off , un til the en/psv input is toggled or v dd is cycled. there is a 5 s delay built into the ovp detector to prevent false transitions. p good is also low after an ovp event. output under-voltage protection when v fb falls 25 % below its nominal voltage (falls to 562.5 mv) for eight consecutive clock cycles, the switcher is shut off and the dh and dl drives are pulled low to tristate the mosfets. the controller stays off until en/psv is toggled or v dd is cycled. v dd uvlo, and por under-voltage lock-out (uvlo) circuitry inhibits switching and tri-states the dh/dl drivers until v dd rises above 3.9 v. an internal power-on reset (por) occurs when v dd exceeds 3.9 v, which resets the fault latch and soft-start counter to prepare for soft-start. the SIC403 then begins a soft-start cycle. the pwm will shut off if v dd falls below 3.6 v. ldo regulator the device features an integrated ldo regulator with a fixed output voltage of 5 v. there is also an enable pin (enl) for the ldo that provides independe nt control. the ldo voltage can also be used to provide the bias voltage for the switching regulator. a minimum capacitance of 1 f referenced to a gnd is normally required at the output of the ldo for stability. if the ldo is providing bias power to the device, then a minimum 0.1 f capacitor referenced to a gnd is required, along with a minimum 1 f capacitor referenced to p gnd to filter the gate drive pulses. refer to the layout guidelines section. ldo start-up before start-up, the ldo checks the status of the following signals to ensure proper operation can be maintained. 1. enl pin 2. v ldo output 3. v in input voltage when the enl pin is high and v in is above the uvlo point, the ldo will begin start-up. duri ng the initial phase, when the ldo output voltage is near zero, the ldo initiates a current-limited start-up (typically 85 ma) to charge the output capacitor. when v ldo has reached 90 % of the final value (as sensed at the fbl pin), the ldo current limit is increased to ~ 200 ma and the ldo output is quickly driven to the nominal value by the internal ldo regulator. ldo switchover function the SIC403 includes a switch-ove r function for the ldo. the switch-over function is design ed to increase efficiency by using the more efficient dc/dc converter to power the ldo output, avoiding the less efficient ldo regulator when possible. the switch-over function connects the v ldo pin directly to the v out pin using an internal switch. when the switch-over is complete the ldo is turned off, which results in a power savings and maximi zes efficiency. if the ldo output is used to bias the SIC403, then after switch-over the device is self-powered from the switching regulator with the ldo turned off. the switch-over logic waits for 32 switching cycles before it starts the switch-over. there are two methods that determine the switch-over of v ldo to v out . t ss = c ss x 1.5 v 2.75 a figure 9 - ldo start-up constant c u rrent start u p v v ldo final 90 % of v v ldo final v oltage reg u lating w ith ~ 200 ma c u rrent limit
www.vishay.com 14 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 in the first method, the ldo is already in regulation and the dc/dc converter is later enabled. as soon as the p good output goes high, the 32 cycl es are started. the voltages at the v ldo and v out pins are then compared; if the two voltages are within 300 mv of each other, the v ldo pin connects to the v out pin using an internal switch, and the ldo is turned off. in the second method, the dc/dc converter is already running and the ldo is enabled. in th is case the 32 cycles are started as soon as the ldo reaches 90 % of its final value. at this time, the v ldo and v out pins are compared, and if within 300 mv the s witch-over occurs and the ldo is turned off. benefits of having a switchover circuit the switchover function is designed to get maximum efficiency out of the dc/dc converter. the efficiency for an ldo is very low especially for high input voltages. using the switchover function we tie any rails connected to v ldo through a switch directly to v out . once switchover is complete ldo is turned off which saves power. this gives us the maximum efficiency out of the SIC403. if the ldo output is used to bias the SIC403, then after switchover the v out self biases the SIC403 and operates in self-powered mode. steps to follow when using the on chip ldo to bias the SIC403: ? always tie the v dd to v ldo before enabling the ldo ? enable the ldo before enabling the switcher ? ldo has a current limit of 40 ma at start-up, so do not connect any load between v ldo and ground ? the current limit for the ldo goes up to 200 ma once the v ldo reaches 90 % of its final values and can easily supply the required bias current to the ic. switch-over limitations on v out and v ldo because the internal switch-over circuit always compares the v out and v ldo pins at start-up, there are limitations on permissible combinations of v out and v ldo . consider the case where v out is programmed to 1.5 v and v ldo is programmed to 1.8 v. after start-up, the device would connect v out to v ldo and disable the ldo, since the two voltages are within the 300 mv switch-over window. to avoid unwanted switch-over, the minimum difference between the voltages for v out and v ldo should be 500 mv. it is not recommended to use the switch-over feature for an output voltage less than 3 v since this does not provide sufficient voltage for the gate-source drive to the internal p-channel switch-over mosfet. switch-over mosfet parasitic diodes the switch-over mosfet contai ns parasitic diodes that are inherent to its construction, as shown in figure 10. there are some important design rules that must be followed to prevent forward bias of these diodes. the following two conditions need to be satisfied in order for the parasitic diodes to stay off. ? v dd ? v ldo ? v dd ? v out if either v ldo or v out is higher than v dd , then the respective diode will turn on and the SIC403 operating current will flow through this diode. this has the potential of damaging the device. enl pin and v in uvlo the enl pin also acts as t he switcher under-voltage lockout for the v in supply. the v in uvlo voltage is programmable via a resistor divider at the v in , enl and a gnd pins. enl is the enable/disable signal for the ldo. in order to implement the v in uvlo there is also a timing requirement that needs to be satisfied. if the enl pin transitions low within 2 switching cycles and is < 0.4 v, then the ldo will turn off but the swit cher remains on. if enl goes below the v in uvlo threshold and stays above 1 v, then the switcher will turn off but the ldo remains on. the v in uvlo function has a typical threshold of 2.6 v on the v in rising edge. the falling edge threshold is 2.4 v. note that it is possible to o perate the switcher with the ldo disabled, but the enl pin must be below the logic low threshold (0.4 v maximum). enl logic control of pwm operation when the enl input is driven abov e 2.6 v, it is impossible to determine if the ldo output is going to be used to power the device or not. in self-powered operation where the ldo will power the device, it is necessary during the ldo start-up to hold the pwm switching off until the ldo has reached 90 % of the final value. this is to prevent overloading the current-limited ldo output during the ldo start-up. however, if the switcher was previously operating (with en/ psv high but enl at ground, and v dd supplied externally), then it is undesirable to shut down the switcher. to prevent this, when the enl input is taken above 2.6 v (above the v in uvlo threshold), the internal logic checks the p good signal. if p good is high, then the switcher is already running and the ldo will run through the start-up cycle without affecting the switcher. if p good is low, then the ldo figure 10 - switch-over mosfet parasitic diodes v out v ldo v 5 v parastic diode parastic diode s w itcho v er mosfet s w itcho v er control
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 15 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 will not allow any pwm switching until the ldo output has reached 90 % of it's final value. on-chip ldo bias the SIC403 the following steps must be followed when using the onchip ldo to bias the device. ? connect v dd to v ldo before enabling the ldo. ? the ldo has an initial current limit of 40 ma at start-up, therefore, do not connect any external load to v ldo during start-up. ? when v ldo reaches 90 % of its final value, the ldo current limit increases to 200 ma. at this time the ldo may be used to supply the required bias current to the device. attempting to operate in self-powered mode in any other configuration can cause unpr edictable results and may damage the device. design procedure when designing a switch mode power supply, the input voltage range, load current, switching frequency, and inductor ripple current must be specified. the maximum input voltage (v inmax ) is the highest specified input voltage. the minimum input voltage (v inmin ) is determined by the lowest input voltage after evaluating the voltage drops due to connectors, fuses, switches, and pcb traces. the following parameters define the design: ? nominal output voltage (v out ) ? static or dc output tolerance ? transient response ? maximum load current (i out ) there are two values of load cu rrent to evaluate - continuous load current and peak load current. continuous load current relates to thermal stresses which drive the selection of the inductor and input capacitors. peak load current determines instantaneous component stresses and filtering requirements such as inductor saturation, output capacitors, and design of the current limit circuit. the following values are used in this design: ? v in = 12 v 10 % ? v out = 1.05 v 4 % ? f sw = 250 khz ? load = 6 a maximum frequency selection selection of the switching frequency requires making a trade-off between the size and cost of the external filter components (inductor and output capacitor) and the power conversion efficiency. the desired switching frequency is 250 khz which results from using component selected for optimum size and cost. a resistor (r ton ) is used to program the on-time (indirectly setting the frequency) using the following equation. to select r ton , use the maximum value for v in , and for t on use the value associated with maximum v in . t on = 318 ns at 13.2 v in , 1.05 v out , 250 khz substituting for r ton results in the following solution r ton = 154.9 k ? , use r ton = 154 k ? . inductor selection in order to determine the indu ctance, the ripple current must first be defined. low inductor values result in smaller size but create higher ripple current which can reduce efficiency. higher inductor values will reduce the ripple current and voltage and for a given dc resistance are more efficient. however, larger inductance translates directly into larger packages and higher cost. cost, size, output ripple, and efficiency are all used in the selection process. the ripple current will also set the boundary for power-save operation. the switching w ill typically enter power-save mode when the load current decreases to 1/2 of the ripple current. for example, if ripple current is 4 a then power-save operation will typically start for loads less than 2 a. if ripple current is set at 40 % of maximum load current, then power-save will start for loads less than 20 % of maximum current. the inductor value is typically selected to provide a ripple current that is between 25 % to 50 % of the maximum load current. this provides an optim al trade-off between cost, efficiency, and transient performance. during the dh on-time, voltage across the inductor is (v in - v out ). the equation for determining inductance is shown next. example in this example, the inductor ripple current is set equal to 50 % of the maximum load current. thus ripple current will be 50 % x 6 a or 3 a. to find the minimum inductance needed, use the v in and t on values that correspond to v inmax. a slightly larger value of 1.3 h is selected. this will decrease the maximum i ripple to 2.9 a. note that the inductor must be rated for the maximum dc load current plus 1/2 of the ripple current. the ripple current under minimum v in conditions is also checked using the following equations. r ton = (t o n - 10 ns) x v i n 25 pf x v out t o n = v out v i n max. x f s w l = ( v i n - v out ) x t o n i ripple l = (13.2 - 1.05) x 31 8 ns 3 a = 1.2 8 h t o n _ v i n mi n = 25 pf x r to n x v out v i n mi n i ripple = ( v i n - v out ) x t o n l i ripple_ v i n = (10. 8 - 1.05) x 3 8 4 ns 1.3 h = 2. 88 a
www.vishay.com 16 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 capacitor selection the output capacitors are chosen based on required esr and capacitance. the maximum esr requirement is controlled by the output ripple requirement and the dc tolerance. the output voltage has a dc value that is equal to the valley of the output ripple plus 1/2 of the peak-to-peak ripple. change in the output ripple voltage will lead to a change in dc voltage at the output. the design goal is that the output voltage regulation be 4 % under static conditions. the internal 500 mv reference tolerance is 1 %. allowing 1 % tolerance from the fb resistor divider, this allows 2 % tolerance due to v out ripple. since this 2 % error comes from 1/2 of the ripple voltage, the allowable ripple is 4 %, or 42 mv for a 1.05 v output. the maximum ripple current of 4.4 a creates a ripple voltage across the esr. the maximum esr value allowed is shown by the following equations. the output capacitance is usua lly chosen to meet transient requirements. a worst-case load release, from maximum load to no load at the exact moment when inductor current is at the peak, determines the requ ired capacitance. if the load release is instantaneous (load changes from maximum to zero in < 1 s), the output capacitor must absorb all the inductor's stored energy. this will cause a peak voltage on the capacitor according to the following equation. assuming a peak voltage v peak of 1.150 (100 mv rise upon load release), and a 10 a load release, the required capacitance is shown by the next equation. if the load release is relatively slow, the output capacitance can be reduced. at heavy loads during normal switching, when the fb pin is above the 750 mv reference, the dl output is high and the low-si de mosfet is on. during this time, the voltage across the inductor is approximately - v out . this causes a down-slope or falling di/dt in the inductor. if the load di/dt is not much faster than the - di/dt in the inductor, then the inductor current will tend to track the falling load current. this will reduce the excess inductive energy that must be absorbed by the output capacitor, therefore a smaller capacitance can be used. the following can be used to calculate the needed capacitance for a given di load /dt: peak inductor current is shown by the next equation. i lpk = i max + 1/2 x i ripplemax i lpk = 6 + 1/2 x 2.9 = 7.45 a rate of change of load current = di load /dt i max = maximum load release = 6 a example this would cause the output current to move from 10 a to zero in 4 s as shown by the following equation. note that c out is much smaller in this example, 254 f compared to 328 f based on a worst-case load release. to meet the two design criteria of minimum 254 f and maximum 9 m ? esr, select two capacitors rated at 150 f and 18 m ? esr. it is recommended that an additional small capacitor be placed in parallel with c out in order to filter high frequency switching noise. stability considerations unstable operation is possible with adaptive on-time controllers, and usually takes the form of double-pulsing or esr loop instability. double-pulsing occurs due to switching noise seen at the fb input or because the fb ripple voltage is too low. this causes the fb comparator to trigger prematurely after the 250 ns minimum off-time has expired. in extreme cases the noise can cause three or more successive on-times. double-pulsing will result in higher ripple voltage at the output, but in most applications it will not affect operation. this form of instability can usually be avoided by providing the fb pin with a smooth, clean ripp le signal that is at least 10 mv p-p , which may dictate the need to increase the esr of the output capacitors. it is also imperative to provide a proper pcb layout as discussed in the layout guidelines section. esr max = v ripple i ripplemax esr max = 9.5 m = 42 m v 2.9 a c out_mi n = l (i out + x i ripplemax ) 2 ( v peak ) 2 - ( v out ) 2 1 2 c out_mi n = 1.3 h (6 + x 2.9) 2 (1.15) 2 - (1.05) 2 c out_mi n = 32 8 f 1 2 c out = i lpk x l x - x dt 2 ( v pk - v out ) i lpk v out i max dl load load dl load dt = 2.5 a s c out = 7.45 x 1.3 h x - x 1 s 2 (1.15 - 1.05) 7.45 1.05 6 2.5 c out = 254 f
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 17 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 another way to eliminate doubling-pulsing is to add a small (~ 10 pf) capacitor across the upper feedback resistor, as shown in figure 11. this capacit or should be left unpopulated until it can be confirmed that double-pulsing exists. adding the c top capacitor will couple more ripple into fb to help eliminate the problem. an optional connection on the pcb should be available for this capacitor. esr loop instability is caused by insufficient esr. the details of this stability issue are discussed in the esr requirements section. the best method for checking stability is to apply a zero-to-full load transient and observe the output voltage ripple env elope for overshoot and ringing. ringing for more than one cycle after the initial step is an indication that the esr should be increased. one simple way to solve this problem is to add trace resistance in the high current output path. a side effect of adding trace resistance is output decreased load regulation. esr requirements a minimum esr is required fo r two reasons. one reason is to generate enough output ripple voltage to provide10 mv p-p at the fb pin (after the resistor divider) to avoid double-pulsing. the second reason is to prevent instability due to insufficient esr. the on-time control regulates the valley of the output ripple voltage. this ripple voltage is the sum of the two voltages. one is the ripple generated by the esr, the other is the ripple due to capacitive charging and discharging during the switchi ng cycle. for most applications the minimum esr ripple voltage is dominated by the output capacitors, typically sp or po scap devices. for stability the esr zero of the output capacitor should be lower than approximately one-third th e switching frequency. the formula for minimum esr is shown by the following equation. for applications using ceramic output capacitors, the esr is normally too small to meet th e above esr criteria. in these applications it is necessary to add a small virtual esr network composed of two capacitors and one resistor, as shown in figure 12. this network creates a ramp voltage across c l , analogous to the ramp voltage generated across the esr of a standard capacitor. this ramp is then capacitive-coupled into th e fb pin via capacitor c c . dropout performance the output voltage adjusts r ange for continuous-conduction operation is limited by the fi xed 250 ns (typical) minimum off-time of the one-shot. when working with low input voltages, the duty-factor limit must be calculated using worst-case values for on and off times. the duty-factor limitation is shown by the next equation. the inductor resistance and mo sfet on-state voltage drops must be included when performing worst-case dropout duty-factor calculations. system dc accuracy (v out controller) three factors affect v out accuracy: the trip point of the fb error comparator, the ripple voltage variation with line and load, and the external resistor tolerance. the error comparator off set is trimmed so that under static conditions it trips when the feedback pin is 750 mv, 1 %. the on-time pulse from the SIC403 in the design example is calculated to give a pseudo-fixed frequency of 250 khz. some frequency variation with line and load is expected. this variation changes the output ripple voltage. because constant on-time converters regulate to the valley of the output ripple, ? of the output ripple appears as a dc regulation error. for example, if the output ripple is 50 mv with v in = 6 v, then the measured dc output will be 25 mv above the comparator trip point. if the ripple increases to 80 mv with v in = 25 v, then the measured dc output will be 40 mv above the comparator trip. the best way to minimize this effect is to minimize the output ripple. figure 11 - capacitor coupling to fb pin v out r 1 r 2 to fb pin c top esr mi n = 3 2 x x c out x f s w figure 12 - virtual esr ramp current c out high- side lo w - side fb pin l r1 r2 r l c l c c duty = t o n (mi n ) t o n (mi n ) x t off(max)
www.vishay.com 18 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 to compensate for valley regulation, it may be desirable to use passive droop. take the feedback directly from the output side of the inductor and place a small amount of trace resistance between the inductor and output capacitor. this trace resistance should be optimized so that at full load the output droops to near the lower regulation limit. passive droop minimizes the required output capacitance because the voltage excursions due to load steps are reduced as seen at the load. the use of 1 % feedback resistors contributes up to 1 % error. if tighter dc accuracy is required, 0.1 % resistors should be used. the output inductor value may change with current. this will change the output ripple and therefore will have a minor effect on the dc output voltage. the output esr also affects the output ripple and thus has a minor effect on the dc output voltage. switching frequency variations the switching frequency will vary depending on line and load conditions. the line variations are a result of fixed propagation delays in the on-time one-shot, as well as unavoidable delays in the external mosfet switching. as v in increases, these factors make the actual dh on-time slightly longer than the ideal on-time. the net effect is that frequency tends to falls slightly with increasing input voltage. the switching frequency also va ries with load current as a result of the power losses in the mosfets and the inductor. for a conventional pwm const ant-frequency converter, as load increases the duty cycl e also increases slightly to compensate for ir and switch ing losses in the mosfets and inductor. a constant on-time converter must also compensate for the same losses by increasing the effective duty cycle (more time is spent drawing energy from v in as losses increase). the on-time is essentially constant for a given v out /v in combination, to off set the lo sses the off-time will tend to reduce slightly as load increa ses. the net effect is that switching frequency increases slightly with increasing load.
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 19 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 SIC403 evaluation board schematic figure 13. evaluation board schematic ton lxbst soft lx vo bst vdd enl pgd fb ilim vin fbl en_psv vout vdd vdd p4 ldtrg p4 ldtrg 1 p8 vin p8 vin 1 c17 220uf c17 220uf m2 m2 1 1 r12 57.6k r12 57.6k c10 220uf c10 220uf c7 0.1uf c7 0.1uf c14 0.1uf c14 0.1uf p5 vctl p5 vctl 1 r15 1.5k r15 1.5k m3 m3 1 1 r8 10k r8 10k r9 * r9 * c11 0.1uf c11 0.1uf b4 vo_gnd b4 vo_gnd 1 j5 probe test pin j5 probe test pin 1 2 5 3 4 p1 vdd p1 vdd 1 r39 0r r39 0r m4 m4 1 1 c5 0.1uf c5 0.1uf c18 220uf c18 220uf p3 step_i_sense p3 step_i_sense 1 c19 1u * c19 1u * c30 100pf c30 100pf c22 220uf c22 220uf c26 4.7uf c26 4.7uf m1 m1 1 1 r23 7k15 r23 7k15 p10 vout p10 vout 1 r1 300k r1 300k r6 100k r6 100k c6 0.1uf c6 0.1uf c24 10n * c24 10n * c16 220uf c16 220uf p11 vo_gnd p11 vo_gnd 1 c2 22uf c2 22uf r29 10k r29 10k c20 220uf c20 220uf r10 10k r10 10k c29 22nf c29 22nf u1 sic401/2/3 u1 sic401/2/3 fb 1 fbl 5 vdd 3 agnd 30 vout 2 vin 6 soft 7 bst 8 vin 9 vin 10 vin 11 nc 14 lx 23 nc 12 pgnd 22 pgnd 21 lx 25 lx 24 pgnd 20 pgnd 19 pgnd 18 pgnd 17 pgnd 16 pgnd 15 enl 32 ton 31 agnd 35 en/psv 29 lxbst 13 ilim 27 pgd 26 lxs 28 lx 33 vin 34 agnd 4 c4 22uf c4 22uf c1 22uf c1 22uf p7 pgood p7 pgood 1 p6 enl p6 enl 1 c13 0.01uf c13 0.01uf q1 si4812bdy q1 si4812bdy c28 0.1uf c28 0.1uf r2 300k r2 300k c37 10nf c37 10nf b2 vin_gnd b2 vin_gnd 1 p9 vin_gnd p9 vin_gnd 1 r7 0r r7 0r c21 10uf c21 10uf c27 4.7uf c27 4.7uf c3 22uf c3 22uf r30 154k r30 154k r5 100k r5 100k r14 100 r14 100 r51 1r r51 1r r13 10k r13 10k l1 0.78uh l1 0.78uh c12 150uf c12 150uf b3 vo b3 vo 1 c15 10uf c15 10uf r52 31k6 r52 31k6 p2 en_psv p2 en_psv 1 r4 1r01 r4 1r01 c36 1nf c36 1nf c25 68pf c25 68pf b1 vin b1 vin 1
www.vishay.com 20 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay siliconix SIC403 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 bill of materials item qty. reference value voltage pcb footprint part number manufacturer 11 b1 v in solder-banana 575-4 keystone 21 b2 v in _gnd solder-banana 575-4 keystone 3 1 b3 vo solder-banana 575-4 keystone 41 b4 v o _gnd solder-banana 575-4 keystone 5 4 c1, c2, c3, c4 22 f 16 v sm/c_1210 grm32er71c226me18l murata 6 1 c5 0.1 f 16 v sm/c_0402 emk105bj104kv-f taiyo yuden 7 1 c6 0.1 f 50 v sm/c_0603 vj0603y104kxacw1bc murata 8 3 c7, c11, c14 0.1 f 50 v sm/c_0603 vj0603y104kxacw1bc vishay 9 3 c10, c20, c22 220 f 25 v 595d-d 593d227x0010e2te3 vishay 10 1 c12 150 f 35 v d8x11.5-d0.6x3.5 eeu-fm1v151 panasonic 11 1 c13 0.01 f 50 v sm/c_0402 vj0402y103kxacw1bc vishay 12 2 c15, c21 10 f 16 v sm/c_1206 c3216x7r1c106m tdk 13 3 c16, c17, c18 220 f 10 v 595d-d 593d227x0010e2te3 vishay 14 1 c19 1 ? sm/c_0603 15 1 c24 10 n ? sm/c_0603 16 1 c25 68 pf 50 v sm/c_0402 0402ya680jat2a avx 17 2 c26, c27 4.7 f 10 v sm/c_0805 lmk212b7475kg-t ta i yo yuden 18 1 c28 0.1 f 10 v sm/c_0603 grm155r61a105ke19d murata 19 1 c29 22 nf 16 v sm/c_0603 murata 20 1 c30 100 pf 50 v sm/c_0402 vj0402y101kxacw1bc vishay 21 1 c36 1 nf 50 v sm/c_0402 c0402c102k3ra vishay 22 1 c37 10 nf 50 v sm/c_0402 vj0402a103kxacw1bc vishay 23 1 j5 probe test pin lecroy probe pin pk007-015 24 1 l1 0.78 h ihlp4040 ihlp4040dzerr78m11 vishay 25 4 m1, m2, m3, m4 m hole2 stacking spacer 8834 keystone 26 1 p1 v dd probe hook - d76 1573-3 keystone 27 1 p2 en_psv probe hook - d76 1573-3 keystone 28 1 p3 step_i_sense probe hook - d76 1573-3 keystone 29 1 p4 ldtrg probe hook - d76 1573-3 keystone 30 1 p5 v ctl probe hook - d76 1573-3 keystone 31 1 p6 enl probe hook - d76 1573-3 keystone 32 1 p7 pgood probe hook - d76 1573-3 keystone 33 1 p8 v in probe hook - d76 1573-3 keystone 34 1 p9 v in _gnd probe hook - d76 1573-3 keystone 35 1 p10 v out probe hook - d76 1573-3 keystone 36 1 p11 v o _gnd probe hook - d76 1573-3 keystone 37 1 q1 si4812bdy 30 v so-8 si4812bdy vishay 38 1 r1 300k 50 v sm/c_0603 crcw060310k0fkea vishay 39 1 r2 300k 50 v sm/c_0603 crcw06030000fkea vishay 40 1 r4 1r01 200 v c_2512 crcw25121r00fkta vishay 41 2 r5, r6 100k 50 v sm/c_0603 crcw0603100kfkea vishay 42 1 r7 0r 50 v sm/c_0603 crcw06030000z0ea vishay
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 21 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 43 3 r8, r10, r29 10k 50 v sm/c_0603 crcw060310k0fkea vishay 44 1 r9 ? sm/c_0603 45 1 r12 57.6k 50 v sm/c_0603 crcw060357k6fkea vishay 46 1 r13 10k 50 v sm/c_0402 crcw040210k0fked vishay 47 1 r14 100 50 v sm/c_0402 crcw040210k0fked vishay 48 1 r15 1.5k sm/c_0603 crcw06031k50fkea vishay 49 1 r23 7k15 sm/c_0603 crcw06037k15fkea vishay 50 1 r30 154k sm/c_0603 crcw0603154kfkea vishay 51 1 r39 0r sm/c_0402 crcw04020000z0ed vishay 52 1 r51 1r sm/c_0805 crcw08051r00fnea vishay 53 1 r52 31k6 50 v sm/c_0603 crcw060331k6fkea vishay 54 1 u1 sic401/2/3 mlpq5x5-32l vishay bill of materials
www.vishay.com 22 document number: 66550 s11-1638-rev. b, 15-aug-11 vishay semiconductors SIC403 new product this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pcb layout of the evaluation board figure 14. top layer figure 16. middle layer 2 figure 15. top component figure 15. middle layer 1 figure 17. bottom layer figure 17. bottom component
vishay siliconix SIC403 document number: 66550 s11-1638-rev. b, 15-aug-11 www.vishay.com 23 this document is subject to change without notice. the products described herein and this document ar e subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package dimensions and marking info vishay siliconix maintains worldwide manufacturing capability. pr oducts may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?66550 . 5.000 0.075 5.000 0.075 + pin # 1 (laser marked) top v ie w a c 0.10 c 0.0 8 c 0.900 0.100 0.050 0.000 b 0.200 ref. bare copper 0.460 0.10 c a b 0.500 0.460 3.4 8 0 0.100 r f u ll 17 24 16 c l c l 9 25 32 8 1.4 8 5 0.100 0.250 0.050 1.660 0.100 bottom v ie w 1.050 0.100 0.400 0.100 r0.200 pin 1 i.d. 1.970 0.100
document number: 64714 www.vishay.com revision: 29-dec-08 1 package information vishay siliconix powerpak ? mlp55-32l case outline notes 1. use millimeters as the primary measurement. 2. dimensioning and tolerances conform to asme y14.5m. - 1994. 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction. 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip. 5. the pin #1 identifier must be existed on the top surface of the package by using i ndentation mark or other feature of package body. 6. exact shape and size of this feature is optional. 7. package warpage max. 0.08 mm. 8. applied only for terminals. b y marking e pin 1 dot top v ie w d (5 mm x 5 mm) 32l t/slp e2 - 2 ( n d-1) xe ref. bottom v ie w side v ie w d2 - 1 r0.200 pin #1 identification b e d2 - 4 d2 - 3 e2 - 3 d4 9 24 25 32 a 0.10 c b 2x 0.0 8 c c a a2 a1 b ( n d-1) xe ref. l 0.36 0.360 5 6 0.10 c a b 4 d2 - 2 e2 - 1 0.10 c a 2x 8 17 16 0.45 1 millimeters inches dim min. nom. max. min. nom. max. a 0.80 0.85 0.90 0.031 0.033 0.035 a1 (8) 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 5.00 bsc 0.196 bsc e 0.50 bsc 0.019 bsc e 5.00 bsc 0.196 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 32 32 nd (3) 88 ne (3) 88 d2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 d2 - 2 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 3 1.00 1.05 1.10 0.039 0.041 0.043 d2 - 4 1.92 1.97 2.02 0.075 0.077 0.079 e2 - 1 3.43 3.48 3.53 0.135 0.137 0.139 e2 - 2 1.61 1.66 1.71 0.063 0.065 0.067 e2 - 3 1.43 1.48 1.53 0.056 0.058 0.060 ecn: t-08957-rev. a, 29-dec-08 dwg: 5983
document number: 91 000 www.vishay.com revision: 11-mar-11 1 disclaimer legal disclaimer notice vishay all product, product specifications and data ar e subject to change without notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicab le law, vishay disc laims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, incl uding without limitation specia l, consequential or incidental dama ges, and (iii) any and all impl ied warranties, including warran ties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of pro ducts for certain types of applications are based on vishays knowledge of typical requirements that are often placed on vishay products in gene ric applications. such statements are not binding statements about the suitability of products for a partic ular application. it is the customers responsibility to validate that a particu lar product with the properties described in th e product specification is su itable for use in a particul ar application. parameters provided in datasheets an d/or specifications may vary in different applications and perfo rmance may vary over time. all operating parameters, including typical pa rameters, must be validated for each customer application by the customers technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product co uld result in person al injury or death. customers using or selling vishay products not expressly indicated for use in such applications do so at their own risk and agr ee to fully indemnify and hold vishay and it s distributors harmless from and against an y and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that vis hay or its distributor was negligent regarding the design or manufact ure of the part. please contact authorized vishay personnel t o obtain written terms and conditions regarding products designed fo r such applications. no license, express or implied, by estoppel or otherwise, to any intelle ctual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners.

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